Non-volatile semiconductor memory devices comprise an array of cells organized in singularly addressable rows and columns. Each cell typically comprises a floating gate MOSFET, a current terminal of which is connected to a bitline and a control terminal of which is connected to a wordline. To establish the logic state of the data stored in a cell, the voltage on the wordline and on the bitline to which the cell to be read belongs is increased. The current that flows through it is compared with the current absorbed by a programmed reference cell.
The diagram of a typical sense amplifier for an EPROM or a FLASH-EEPROM memory device is depicted in FIG. 1. The sense amplifier comprises a bitline current path, a reference current path, and an equalization circuit for eventually comparing the currents circulating in the two paths.
The bitline current path includes the pre-charge transistor M6 and the bitline selection transistors M4 and M2 respectively controlled by the logic gate NR2, by the inverted enable signal ENABLE_N and by the selection signal Y0 for the memory cell selected to be read (not depicted in figure) that absorbs a current ICELL. The reference current path includes NR1, M5, M3, M1 and the reference cell (not depicted) and is identical to the bitline path but is activated by the respective inverted enable signal RFENABLE_N. If the cell to be read is not programmed, ICELL>IREF and if the cell is programmed ICELL<IREF.
The sense amplifier further comprises a current mirror M8, M9 that functions as a current-to-voltage converter for developing voltages on its input nodes REF and output nodes MAT corresponding to the currents IREF and ICELL, respectively. These voltages are then compared by a comparator that generates a logic signal DIFFOUT that is buffered (SAOUT) by a cascade of two inverters. The logic signal DIFFOUT indicates whether the read cell is programmed or not.
A desired feature of the sense amplifiers is that of rapidly generating a pre-established voltage on the node MAT for comparing this voltage with the voltage on the node REF as fast as possible for reducing the time of evaluating a memory cell. Sense amplifiers typically comprise an equalization line, which in FIG. 1 includes the MOSFET M7, for making equal the voltages on the nodes REF and MAT before starting a read operation. Therefore, the voltage on the node MAT is at a value relatively close to the voltage REF before the cell state is evaluated, and may quickly reach the level corresponding to the programmed or to non-programmed state of the cell.
Different forms of equalization lines, even more complex than the one depicted in FIG. 1, are known. They all have the function of making equal the potentials of certain “critical” nodes of the sense circuit (in the depicted example the nodes MAT and REF) before the evaluation step. This is done to speed up the production of the comparison signal DIFFOUT between the voltages sensed on the nodes MAT and REF once the equalization line is disabled by the control signal SAEQ at the appropriate instant.
This time instant is defined in consideration of the charging of the capacitances of the selected bitline and wordline. The equalization line is disabled when the voltages on the selected rows and columns have reached the steady-state value or at least a value that will ensure that the evaluation will not be affected by uncertainty. Obviously, this depends on the time constant RC associated to the bitline and wordline current paths of the memory.
The timing of the signal SAEQ is determined for the reading speed of the memory. For this reason, memory devices are provided with delay networks trimmable by metal-fuses or by UPROM based upon the use of dedicated dummy lines.
The sense amplifier of FIG. 1 has various drawbacks. The first drawback is due to the capacitive coupling between the nodes MAT and REF when SAEQ switches low opening the switch M7. The second drawback is the need of having a reference path for each sense amplifier dedicated to each data output. This significantly complicates the circuit (distribution of the reference current) and results in a large area of silicon being used.
The third drawback is a relatively large pre-charge time of the bitlines and wordlines. The voltages on the selected row and column should reach the stand-by value before the signal SAEQ may switch. Otherwise, there will be a transient due to the difference between the current flowing in the array cell ICELL and the current flowing in the I/V converter resulting in a time loss.